The present invention relates to the design of semiconductor integrated circuits or xe2x80x9cchipsxe2x80x9d. In particular, the present invention relates to a method and apparatus for efficiently debugging chips during chip design.
During the design of silicon based chips such as microprocessors, digital signal processors and the like, debugging procedures permit chip designers to verify the configuration and operation of a chip as well as to correct problems with the chip that may arise during the design process. Generally, a chip design includes a large number of Input/Output (I/O) ports which connect the chip to a processor board or a module for integration into an overall system. The number of I/O ports for a given chip design may be in the hundreds, although typically, only a small portion of the I/O ports are available for debugging the chip design. The limited number of I/O ports available for debugging makes the nature of chip design/debugging difficult, particularly when a chip design employs address buses, data buses and control signals that are spread across multiple clock domains.
Complex chip designs typically require the use of a myriad of debugging logic. Such debugging logic can represent a significant amount of a chip""s hardware, and can consume a large amount of physical area and capacity of a chip. As a result, less hardware, physical area and capacity of the chip may be dedicated to the logic circuitry required to perform the chip""s intended operations. For example, large multiplexers are often employed to multiplex debug signals over each of the limited number of debug I/O ports present in a chip design, resulting in processor redundancy and resource waste.
In view of the foregoing, it would be desirable to eliminate the redundancy resulting from multiplexing every debug I/O port. Moreover, it would be desirable to simplify debug logic circuitry such that less chip hardware, area and capacity are dedicated to debugging.
In accordance with a first aspect of the invention, an apparatus is provided that is adapted to multiplex debug signals of an integrated circuit. The apparatus includes at least a first multiplexing circuit and a second multiplexing circuit. The first multiplexing circuit is adapted to receive first debug signals from the integrated circuit and to selectively multiplex at least a first portion of the first debug signals onto a first bus. The second multiplexing circuit is adapted to receive second debug signals from the integrated circuit and to selectively multiplex at least a first portion of the second debug signals onto a second bus. The apparatus further includes a logic circuit adapted to combine any debug signals of the first bus and any debug signals of the second bus onto a third bus. An output stage of the apparatus is adapted to selectively output debug signals of the third bus.
In at least one embodiment of the invention, the output stage may include a third multiplexing circuit adapted to receive debug signals of the third bus and to selectively multiplex the debug signals onto a fourth bus. Numerous other aspects of the invention are provided, as are systems and methods for carrying out these and other aspects.
Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.